The standard for soft error prevention - IROC Technologies

TSMC 2013 OIP

olivier — Mon, 10 Jun 2013 21:40:14 +0000

iROC will be at TSMC 2013 Open Innovation Platform Ecosystem Forum being held on Tuesday, October 1st at San Jose McEnery Convention Center. Visit our booth (#314).

Article on Journal of Electronic Testing

olivier — Fri, 07 Jun 2013 16:34:47 +0000

iROC’s “A Practical Approach to Single Event Transient Analysis for Highly Complex Design” has just been published and is available here.

Watch Webinar

olivier — Thu, 30 May 2013 22:03:38 +0000

If you missed the live webinar, here’s the recording of “Do I Need to Worry About Soft Errors?”

The slides are also available at SlideShare

DAC ’13 Schedule (Booth #1738)

olivier — Thu, 30 May 2013 21:33:08 +0000

There are three ways to meet us at DAC 2013.

iROC will exhibit at DAC 2013 at Booth #1738. For more information, click here
iROC will present at Designer Track on June 4th, 2013.
iROC will present in TSMC Open Innovation Platform® Theater;

6/3 – Monday, 1:45 – 1:55 pm
6/4 – Tuesday, 11:45 – 11:55 am
6/5 – Wednesday, 10:00 – 10:10 am

Paper at MEDIAN’13 on 5/30/13

olivier — Thu, 30 May 2013 21:25:37 +0000

iROC Technologies is pleased to announce that Enrico Costenaro is presenting a paper titled “A Standards Based Approach to the Reliability Specification of IP Components” at the Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN ’13) Workshop in Avignon, France on May 30, 2013. Click here to view the Workshop schedule.

Test White Paper

olivier — Wed, 29 May 2013 23:13:02 +0000

There are many good reasons to perform radiation testing. For companies with little experience managing soft error effects (SEEs), soft-error testing enables them to:

See how they rank for SEE performance (from single component to whole system)
Identify the most sensitive components in a system in order to focus on the most important elements for improving the overall system SER performance.

For companies with a strong SEE strategy:

Validate the expected final performance of their product after SEE aware design
Monitor SER performance of their products over time
Test performance of external suppliers

Benchmark the performance of competitors for marketing purposes

SoCFIT White Paper

olivier — Wed, 29 May 2013 23:11:51 +0000

Most designers of complex silicon devices have a basic awareness of soft-error (SER) effects; however, fewer know how to specify reliability requirements for their SoC and to analyze whether their design meets the requirements. A SEE (single-event effect) is the result of a natural, sub-atomic particle hitting the semiconductor material and depositing charge in the sensitive regions of a circuit. An important percentage of SEEs are discarded or masked without further impact on the circuit operation, however, a subset of SEEs propagate, becoming soft-errors and causing serious impacts such as server crashes, silent data-corruption (SDC) or incorrect system actions. When these events occur in the field, they result in product returns, unmet service level agreements (SLAs) and dissatisfied customers. It is essential to accurately calculate the fraction of soft-errors that have user-visible impacts in order to ensure product reliability targets are met. Designers aware of the problem usually protect RAMs from soft errors using Error Correcting Codes (ECC), but mitigating flip-flops soft-errors remains a challenge and effective generic and cost effective solutions do not exist.

TFIT White Paper

olivier — Wed, 29 May 2013 23:09:24 +0000

The most obvious profile of TFIT users are cell designers. They can either be at a foundry, an IP developer or IDM/fabless designing their own libraries. It is their job to predict the performance of each cell at all the possible operating points and conditions: voltage, temperature, process, drive strength.

iROC webinar on 5/30/13

olivier — Fri, 24 May 2013 22:21:21 +0000

Adrian Evans will present a short webinar titled as “Do You Need to Worry About Soft Errors?”

The webinar starts at 11:30 am PST on Thursday May 30th. To register, please click here.

SESSION 3: DESIGNER TRACK at DAC 2013

olivier — Mon, 20 May 2013 17:43:34 +0000

DAC 2013 is just weeks away. Please come check iROC’s presentation during DAC 2013.

SESSION 3: DESIGNER TRACK (more info)
Poster Session 1
Tuesday, June 4, 2013
Time: 12:00 PM — 1:30 PM
Location: Hall 5
Topic Area: Designer Track

3.34 — Reliability by Design – Balancing Reliability, Complexity, and Verification

Speaker:	Adrian Evans - iRoc Technologies, Grenoble, France
Authors:	Adrian Evans - iRoc Technologies, Grenoble, France
	Dan Alexandrescu - iRoc Technologies, Grenoble, France
	Enrico Costenaro - iRoc Technologies, Grenoble, France
	Olivier Lauzeral - iRoc Technologies, Mountain View, CA