The standard for soft error prevention
Single Event Effects are influenced by design, technology process and application running on the chip.
For an optimal approach, designers need to address the issues along these three dimensions.
Thanks to our partnership with foundries, our prediction tools model the intimate behavior of process technologies to
your design for accurate SER prevention.
SEE prediction and mitigation concerns foundries, cell designers, reliability engineers and SoCarchitects.
We offer two different tools that address these user-specific needs and development environments:
- TFIT for cell library developers
- SOCFIT for SoC architects.
TFIT uses the foundry’s process response model as technology input and spice netlist and GDS2 as design input. Application for a cell are voltage, clock speed, presence of
ECC and are user input through the GUI.
SOCFIT uses the SER database of cells SER perfomances as technology input (output from TFIT) and the RTL/netlist as design input. Application input through vector files.
- Cell level
- Circuit level