SOCFIT™: Circuit Level Soft Error Analysis

Assess Soft Error Risk During Design

As Soft Error threat increases in latest technology process nodes (65nm and below), various industries are in need to investigate this serious reliability issue. IROC Technologies, a world expert in the field, has developed in the past 10 years solutions for the analysis and test of radiation-based Soft Error issues.

Within these solutions is the SOCFIT software, an EDA tool that predicts quickly and accurately the failure rate (FIT) and various derating factors of ASIC and SoC, using either RTL or Gate Netlist representation.

SOCFIT uses the intrinsic sensitivities of each feature of the circuit.

We offer access to this tool either through SW licensing or as a design service from IROC experts.

OVERVIEW

• EDA software platform using genuine foundries SER
  database for FIT and derating simulation. Works on very
  large designs (10s of millions FF)
• Includes analysis of application, time and logic
  deratings.
• Extensive report: contribution of each cell to the
  overall FIT rate, details of derating.
• Effective and smart fault injection simulation for
  application derating
• Performed either at IROC or within your environment with
  remote access to IROC

YOUR INPUT:

• Circuit RTL or gate level Netlist description
• Timing files (for Netlist analysis)
• Application specific vectors for simulation

SOCFIT MODULES AND ENVIRONMENT NEEDS:

SOCFIT is a unique simulation platform that interacts with existing static timing analysis and simulation/verification tool (like SNPS VCS).