Enabling Lifetime Performance – by Dan Alexandrescu
There are many interesting challenges associated to the aging of semiconductor devices. The industry and its R&D partners needs a very good understanding of the phenomena, the supporting EDA infrastructure and efficient solutions to implement advanced self-tuning devices able to work reliably over the projected lifetime of the system.
An important requirement is that today’s devices are expected to function correctly during the projected circuit lifetime, without failures or performance degradation, over a large range of operating conditions and workloads. A key aspect of this continuous expected reliability is semiconductor aging. Phenomena such as Hot Carrier Injection and Bias Temperature Instability can change the electrical properties of the transistors and gates altering the performance of the device. The aging problem is getting worse with aggressive technology scaling, process variations, dynamic operating ranges and increased circuit complexity and size.
The semiconductor industry needs efficient solutions to manage aging issues in today’s sophisticated devices. Firstly, technology providers and device physics experts are working hard to provide a clear understanding of the physical phenomena and its impact on the characteristics of the transistors and gates. Furthermore, aging information needs to be propagated in the design and manufacturing flow (through the adequate reliability data exchange formats – such as RIIF [1]) to be used by designers and systems architects during the specification and implementation of the reliability features of the system. Obviously, EDA tool support is an undisputed requirement for any data exchange, aging analysis or improvement.
Therefore, the collaboration of all the partners from the design and manufacturing flow is absolutely needed. As an example of such process, the MoRV project [2] is a R&D undertaking focused on semiconductor aging and process variability integrating experts on technology, device physics, circuit and system designers, EDA tools providers and end-users. The overall goal of the project is to provide accurate aging models of transistors, logic gates and blocks, predicting the design performances over the projected lifetime.
The next step consists in managing the aging issues allowing continuous reliable system operation at the required performance levels. Degradations affecting the delays of the standard cells can be mitigated through guard-banding. Particularly, one-time worst-case guard-bands are typically added by designers during the specifications or design flow. Obviously, reducing the guard-bands is a critical issue for the semiconductor industry, from a performance or competitive perspective. Accurately characterizing the circuit aging is a requirement for an effective and frugal guard-banding.
However, removing the guard-bands completely is even more attractive for the industry. Techniques based on self-calibration and self-tuning can progressively compensate circuit aging over the circuit lifetime. In addition, these techniques are the key for continuous performance, reliability and lower power consumption in today’s power-conscious mobile and high performance computing.
Self-calibration and self-tuning techniques consist in dynamically adjusting various system and local parameters (such as voltage, frequency, biasing) to the performance requirements, workloads, environment and aging. They rely on physical data provided by embedded test instruments, sensors and monitors. The academic and industrial research community provides a wealth of solutions [3] to detect or predict timing errors induced by aging.
Of a particular interest to the industry, pre-error monitoring and error detection can be implemented using double-sampling architectures [4]. This approach allows detecting temporary faults (timing faults, transients, upsets) at very low cost and can be used to adapt the clock frequency of the circuit to the degradation of the circuit delays, supporting a successful implementation of the self-tuning approach. Double sampling architectures help mitigating numerous flaws concerning nanometric technologies, such as: PVT variations, accelerated circuit aging, EMI, soft-errors, power dissipation, and thermal issues.
In conclusion, there are many interesting challenges associated to the aging of semiconductor devices and the industry needs a very good understanding of the phenomena, the supporting EDA infrastructure and efficient solutions to implement advanced self-tuning devices able to work reliably over the projected lifetime of the system.
[1] Evans, A.; Nicolaidis, M.; Shi-Jie Wen; Alexandrescu, D.; Costenaro, E., “RIIF – Reliability information interchange format,” On-Line Testing Symposium (IOLTS), 2012 IEEE 18th International , vol., no., pp.103,108, 27-29 June 2012[2] MoRV, “Modelling Reliability under Variability”- http://morv-project.eu
[3] ELESIS R&D project – http://www.elesis.eu/, RESIST R&D project – http://www.resist-catreneproject.eu/
[4] Nicolaidis, M., “Double-sampling architectures,” Reliability Physics Symposium, 2014 IEEE International , vol., no., pp.3D.1.1,3D.1.7, 1-5 June 2014