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Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems – March 18th 2016 – Dresden, Germany

IROC is co-organizing the ERMAVSS Workshop.

Together with  Stefano di Carlo (Politecnico di Torino – IT), Praveen Raghavan (IMEC – BE) and Dimitris Gizopoulos (University of Athens – GR), IROC’s Adrian Evans is the General Chair Co-Chair

With the proliferation of integrated circuits implemented in the most advanced process technologies, there is a growing need to jointly analyze the effect of multiple sources of failures including variability and aging and to understand, early in the design cycle, their impact on system reliability. Today, conservative margins are required to ensure that devices operate correctly over their full lifetime, despite the impact of aging effects (BTI, HCI) and failure mechanisms such as EM. New methodologies for improved cross-layer modeling and mitigation, if planned early in the design of a product, have the potential to remove unnecessary conservatism, reduce power and cost and improve yield. This workshop is focused on sharing new research on techniques and methodologies for modeling the effects of failures due to transistor aging, variability and other mechanisms all the way from the cell level to system level. New approaches to perform early estimations of system reliability are much needed to enabling reliable, optimized and low-power designs.

Link to event