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Extending UVM Verification Models for the Analysis of Fault Injection Simulations

In high-reliability and safety-critical applications, RT and gate-level fault-injection simulations are often performed in order to ensure a certain level of fault detection coverage which is necessary to ensure compliance with standards such as ISO 26262. There are many techniques available for accelerating the simulations including emulation platforms, however, in most cases, classifying the failing scenarios remains a manual task and is often the limiting factor in the number of fault injections that can be performed.

In this article, we show how the components of a UVM functional verification environment can easily be extended to record additional information about the types of errors that have occurred. This additional information can be used to classify failing tests based on their system level impact (e.g. Silent Data Corruption, Detected Uncorrected Error, etc.). We present an architecture that can be implemented on Mentor’s Questa® Verification Platform for designs with UVM DVE.

For further info and the complete paper please go to Mentor Graphic’s Verification Horizons