TFIT™: Cell Level Soft Error Analysis
Whether it is to fully characterize quickly a whole cell library for Soft Error sensitivity at every corner, or to design a new Flip Flop with better immunity to external radiations, TFIT has all the needed features:
– neutron impact analysis (terrestrial flux, or other customized spectrum)
– alpha particle, thermal neutrons, heavy ions impact
– Single bit upset or multi bit upset analysis
– automatic GDS2 analysis for layout parameters extraction
– charge sharing effect
– Angular impact analysis
The tool is offered through SW licensing or as a design service from IROC experts.
TFIT licensees can get access to specific technology models by contacting their foundry (our partners) for process from 65nm to FinFET.
OVERVIEW
- Very fast Soft Error prediction EDA tool: seconds to minutes for complex simulations
- Works for memories, FF, registers, combinational cells
- Accurate results: within 15 % of silicon test results
for many radiation environments - Extensive report: detail of FIT per transistor. Mapping
of cell sensitivity per particles’ LET. Helpful for quick
design improvement - Services available – to be performed at IROC or within your design environment with remote access for IROC engineers
Heavy Ion Strike – normal incidence angle
Heavy Ion Strike – 80 degree incidence angle
Required INPUT:
- Cell netlist (including parasitic elements)
- Process node
- Spice model of transistors
- Layout information (from GDS2 or equivalent)
- Specific environment (neutrons, alpha particles, heavy ions)
- Application information: Vdd, clock frequency, ECC
TFIT has been co-financed by the European Union.