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TFIT Case Study

TFIT™: Case Study Soft Error Analysis


A large fabless specialized in designing chips that are used in large routers and computer farms, is working on its new design in 28nm.

Its end customer issued a specification for Soft Error performance which is a list of types of radiation-generated failures and the corresponding FIT or Failure in Time. Indeed, each failure can have a different impact on the overall system reliability. Furthermore, each error can be mitigated at various levels, using software procedures, system architecture optimization or simply by improving the reliability performance of the chip.

Fabless’s concern is to meet that reliability performance for their latest 28nm SoC design.

Traditionally post silicon method were used (radiation testing) but it is costly, difficult and long to implement, and happens too late for any type of change. It is a solution for verification, but can’t be used as a proactive optimization process of the design.

Prediction by analysis and prevention are the most cost effective approaches and sometimes the only ones that designers can implement.

Fabless can use SoCFIT™ simulation platform to run such analysis on a gate netlist or even better on the design’s RTL description. Modifications are still possible at manageable cost when the problem is dealt with before synthesis. But RTL is not the only input necessary to run an accurate analysis.

Soft Errors have three main sources: technology, design and application.

Optimization of the combination of the three is necessary to get the best cost effective solution. Sometimes application is the least flexible part as it is the end customer’s property and out of reach for the fabless. RTL is the design part of the input. The technology side is a database of FIT (Failure In Time) rate for each individual cell (SRAM, FF, combinational logic) used in the design for the particular environment the chip will be used in.  They are the intrinsic FIT values of the cells.


There are multiple ways to get to the cells’ FIT number.

One is radiation testing, but again it requires access to silicon samples, to radiation beam lab and to experience of such a complicated test.

Another more time and cost effective way is simulation. TFIT™ is the perfect tool for this. Actually TFIT can not only predict the FIT rate for the cell, but it is also a tool for layout optimization to improve the FIT performance.

Again, like for SOCFIT and SER at chip level, the FIT rate at cell level depends on the combination of three elements: design of the cell, the process technology and the application.

For a cell the application is mostly the voltage, whether it uses ECC or some error protection scheme and to a lesser extent some timing input.

Cell design is described in TFIT with the cell SPICE netlist and the layout (GDS2 or other graphical representations).

The environment is described directly by the user through the TFIT GUI: type of particle, energy ranges. If unknown, TFIT proposes the most relevant data input, so the user doesn’t have to be a specialist.

The technology input to TFIT is called the response model. This model characterizes a foundry’s particular technology node. For example TSMC 40G or GLOBALFOUNDRIES 40HP. Presence of DNW or not is also very relevant to the result and is embedded into the model. When running an analysis with TFIT, the user is asked to input the cell Netlist and which is the technology response model it will be manufactured with. Another important technology input is the transistor spice mode, which is also an input from the foundry.

Besides Cell netlist, the way design is described in TFIT is through some specific dimensions from the layout: distances between drains of different transistors, sharing of charge collection areas. This is user’s manual input.

TFIT simulation is very fast and very accurate. It takes 3 minutes to simulate an SRAM cell (6 T) and the accuracy is within 10 to 15% of the neutron test results.

This is within one standard deviation of the test, so test and simulation cannot statistically be differentiated. This accuracy and speed allow the user to run trial and error analysis by making small variations to their design and see the evolution of the FIT.

Another nice feature of the tool is the visualization of the cross sections (or sensitive area) per type of particle (or LET: Linear Energy Transfer) on the cell layout.

Designers then can understand what are the weak points of their design and try out some modifications. Another valuable output of the tool is the MCU analysis module, or Multi Cell Upset. MCU are mostly for memories and are caused by one single particle. While very rare in older technologies, it is one of the fastest growing threats at smaller nodes.

TFIT MCU report shows the MCU rate and the most likely patterns, helping memory designers to optimize scrambling.

TFIT is a user friendly tool and can be used by non specialists. It takes few hours or training for a design engineer to be trained and get a workable knowledge of the tool.

With the growing set of existing response model describing a wider set of geometries, TFIT is the Industry standard for cell level SER analysis.