IROC Technologies is thrilled to announce the upcoming release of the latest version of SoCFIT, an ultra-fast EDA solution designed to analyze and mitigate soft errors in complex digital circuits. Essential for high-reliability applications, SoCFIT helps you meet stringent functional safety standards by identifying critical circuit weakness from the earliest stages and throughout the design cycle.
SoCFIT is a cutting-edge solution for understanding the soft errors propagation in IP blocks or entire SoCs and providing efficient mitigation strategies by classifying vulnerable elements. Whether you’re working on automotive, aerospace, HPC, medical or other high-reliability projects, SoCFIT ensures your designs are reliable and achieve your target FIT rate.
Key features include:
* Comprehensive error propagation analysis: evaluates fault propagation based on circuit structure and simulation vectors
* Detailed vulnerability reporting: computes Logical (LDR), Temporal (TDR), Functional (FDR) De-Rating/Vulnerability Factors
* Broad design language support: compatible with SystemVerilog, Verilog, and VHDL, fitting seamlessly into your existing workflows
* Scalable for large design: handles over 1 million flip-flops per partition, bottom-up approach makes it ideal for even the most complex SoC
* Ultra-fast simulation: achieves over 1000X faster simulations than typical approaches, drastically reducing analysis time
* Extensive reporting: generates detailed reports highlighting the contribution of each cell, module, and instance to the overall FIT rate
* Efficient mitigation strategies: provides clear guidelines for mitigating vulnerabilities, helping you develop robust and reliable designs
The new version of SoCFIT includes, FDR FastSIM, an ultra-fast fault propagation simulation engine. It allows an efficient Functional De-Rating analysis about 1000 times faster than conventional methods. Designed to integrate seamlessly into the whole digital design flow, SoCFIT significantly improves end-product reliability by mitigating transient fault threat early. Its advanced features and speed make it ideal for handling even the most complex SoC designs, maintaining accuracy and efficiency throughout the process.
The latest version of SoCFIT will be available at the end of June. Stay tuned for more details and get ready to take your SoC designs to new levels of reliability.
To learn more and request a demo, please contact us at sales@iroctech.com.
We are planning to attend DAC, The Chips to Systems Conference at the end of June. Visit our booth #2557 to discuss SoCFIT and learn more about our offerings including TFIT for cell-level soft error analysis, radiation testing and consulting services. This is a great opportunity to see our EDA tools in action and discover how they can enhance your design process.
